1. Technical Field
The present invention relates generally to the field of integrated circuit design, and, more specifically, to the field of logic synthesis of electronic circuit designs. Yet more specifically, the present invention relates to a method, system, and computer program product for improving wireability near dense clock nets.
2. Description of Related Art
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. The process of converting the functional specifications of an electronic circuit into a layout is called the physical design.
The objective of physical design is to determine an optimal arrangement of devices in a plane or in a three dimensional space, and an efficient interconnection or routing scheme between the devices to obtain the desired functionality.
An integrated circuit chip (hereafter referred to as an xe2x80x9cICxe2x80x9d or a xe2x80x9cchipxe2x80x9d) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
A net is a set of two or more pins which must be connected. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins which must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. All the pins of a net must be connected. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins.
The input to the physical design problem is a circuit diagram, and the output is the layout of the circuit. This is accomplished in several stages including partitioning, floor planning, placement, routing and compaction.
Placement of logic blocks involves first obtaining information defining a logic block. The information includes the actual physical dimensions of the logic block. An appropriate amount of physical space is then allocated within which to place the logic block.
Due to the large number of components and the exacting details required by the fabrication process, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use Computer Aided Design (CAD) tools.
When a placement tool is used, a physical size of each logic block is determined. The logic block is placed in an area which is large enough for the particular logic block. Routing is then completed. Modern synthesis tools interact with the placement of the logic as they make optimization choices in the logic, including how the clocks are distributed to the latches in the logic.
Routing near dense clock distribution blocks, such as local clock buffers (LCB), can be difficult. These dense clock nets occur when many latches are located near the LCBs. The problem is compounded for particular types of LCBs which use three clocks, a master, slave, and scan clock. In addition, the latches tend to use a lot of low level metal in their internal wiring, adding even more to the congestion and making their logic pins hard to access on that low level of metal.
Therefore, a need exists for a method, system, and product for improving wireability near dense clock nets.
A method, system, and computer product are disclosed for improving wireability near clock nets in a logic design that includes multiple logic blocks. Each of the logic blocks has an actual physical size. Logic blocks that are a particular type are identified Dining placement of the logic blocks, an apparent physical size of each of the identified logic blocks is utilized as a physical size for the identified logic block. The apparent physical size is larger than the actual physical size. During routing, the actual physical size of each of the identified logic blocks is utilized
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.